Symmetrical all-magnetic shift registers



sheet l of 9 G. W. DICK :i1 kr Nm SYMMETRICAL ALL-MAGNETIC SHIFTREGISTERS June 24, 1969 Filed July 21, 1965 EN W Q2) NN 3N N www Afro/wer n@ \\\l l E ,W h .1 l u] M /wm n @gmc @Y w SK.. KY @t June 24,1969 G. w. DICK 3,452,335

SYMMETRICAL ALL-MAGNETIC SHIFT REGISTERS June 24, 1969 G,W D|CK 13,452,335

SYMMETRICAL ALL-MAGNETIC SHIFT REGISTERS Filed July 21, 1965 Sheet of 91 .UT/DUT June 24, 1969 G w D|CK SYMMETRICAL ALL-MAGNETIC SHIFTREGISTERS Filed July 21, 1965 Sheet June 24, 1969 G, W D|CK SYMMETRICALALL-MAGNETIC SHIFT REGISTERS Sheet Filed July 2l, 1965 June 24, 1969 3G. w. DICK SYMMETRICAL ALL-MAGNETIC SHIFT REGISTERS Filed July 2l, 1965G ors Sheet -Sheet of 9 June 24, 1969 G, W D|K SYMMETRICAL ALL*MAGNETICSHIFT REGISTERS Filed July 21, 1965 June 24, 1969 G. w. DICK 3,452,335

SYMMETRICAL ALL-MAGNETIC SHIFT REGISTERS Filed July 21, 1955 sheet 9 of9 nted States 'Patent O U.S. Cl. 340-174 30 Claims ABSTRACT F THEDISCLOSURE A family of all-magnetic shift registers is shown, includingboth toroidal core and multiapertured core embodiments. The lowest phaseorder embodiment is a threephase shift register wherein three toroidalmagnetic cores are utilized for storing information in each bitposition, and all-magnetic coupling arrangements are provided amongthose cores and between stages of the register. Design rules forextending the underlying shift register operating principle to systemsof higher phase orders are presented and are applied in connection witha four-phase shift register. The rule of operation of these registers isthat in an m phase circuit, including storage elements arranged in apredetermined sequence, the shifting of one storage element from a firstto a second bistable condition causes the (m-l)th element following theshifting element in the sequence to be shifted into its first conditionif it was not already in that condition. This type of operation takesplace without disturbing intermediate storage elements.

This is a continuation-in-part of my prior copending application Ser.No. 199,371 which was tiled June l, 1962, and has been abandoned. Theinvention relates to controlled all-magnetic logic networks, and it hasparticular reference to such logic networks which may be emv ployed inall-magnetic shift registers.

The use of magnetic devices in many logic circuit applications isbecoming increasingly popular. One Widespread application for magneticcircuit devices is in the shift register tield, and in that field anincreasing amount of effort is being directed toward improvements inshift registers utilizing only magnetic elements and interconnectingelectric circuit leads. No conventional currentcarrying circuit elementsare included in such a shift register, which is commonly designated anall-magnetic shift register.

It has heretofore been the practice to arrange the basic logic blockscomprising a shift register stage so that a minimum of four phases ofshift register operation were required in all-magnetic shift registersin order to move information bits through a stage of the register withappropriate buffering to prevent intersymbol interference. In some priorart circuits the four phases of shift register operation are controlledby four phases of externally applied control signals. In other circuits,however, only a part of the phases of operation are controlled byexternally applied control signals, and the remaining phases ofoperation are controlled by the nature of operation of certain shiftregister circuit magnetic elements. In all cases, however, the knownprior art circuits require a minimum of four time phases to cycle aregister stage completely, and this requirement imposes a restrictionupon the maximum speed of operation.

It is, therefore, one object of the invention to improve all-magneticlogic networks.

An additional object is to increase the potential operating speed ofall-magnetic shift registers.

It is another object to operate an all-magnetic shift register stagewith less than four time phases for a cycle of operation.

An additional object is to improve operating margins for all-magneticlogic networks.

These and other objects of the invention are realized in an illustrativeembodiment wherein plural magnetic devices are coupled together to forma three-phase logical network with at least two input circuits and anoutput circuit. This network is responsive to first and secondsuccessive input signals of different predetermined polarities on oneinput circuit, followed by a third signal of a predetermined polarity onthe other input circuit, for producing in the output circuit incoincidence wit-h the second and third signals two successive signals ofthe aforementioned different predetermined polarities. Within thenetwork are a two-state magnetic storage device, with set and resetstates, and electromagnetic coupling means with two-state input andoutput portions. The two portions are operatively coupled together andoperatively coupled to the storage -device in opposite senses so thatthe setting of the input portion also sets the storage device and theresetting of the input portion also sets the output portion. Theaforementioned one input circuit of the network is coupled to thecoupling means input portion, and the other input circuit is coupled tothe storage device and the coupling means output portion.

A plurality of the described logical networks are connected in a tandemsequence of a three-phase shift register. Shift signals are successivelyapplied to the devices in the sequence of the tandem connection toswitch the storage devices of the sections to their reset conditions.The resetting of each storage device causes the coupling means to setthe storage device in the second following section of such tandemsequence without altering the stable condition of the storage device inthe intermediate section.

It is one feature of the invention that the network coupling meansassociated with each pair of networks is arranged so that theapplication of a shift signal to reset the storage device of a first oneof such networks in the sequence enables the output portion of thecoupling means to participate in the propagation of resulting signalsthrough the shift register but simultaneously disables such portion forpropagating to other networks any signals appearing in the couplingmeans of either network of the pair which tend to set the storage deviceof such network.

It is another feature of the invention that as few as three time phasesare advantageously utilized for driving a shift register stage through acomplete cycle of operation with appropriate buffering betweeninformation bits to prevent intersymbol interference.

A further feature is that the three-phase logical network of theinvention is the lowest ordered one of a family of readily derivablelogical networks of higher numbers of phases and which display improvingoperating margins with increasing phase order of the register.

A full understanding of the invention and the various objects andfeatures thereof may be obtained from the following description and theappended claims when considered in connection with the attached drawingswherein:

FIG. l is a partial schematic diagram of a shift register in accordancewith the invention;

FIG. 2 is a schematic diagram, using mirror symbology, of the shiftregister of FIG. l;

FIG. 3 is a diagram of the binary conditions of magnetic devices in theshift register of FIG. 1 illustrating the operation of the invention;

FIGS. 4A and B are timing diagrams of shift and bias signals foroperating the circuit of FIG. 2;

FIG. 5 is a more complete schematic diagram of one stage in the shiftregister of FIG. l;

rice

FIG. 6 is another embodiment of the invention utilizing multiaperturemagnetic devices;

FIGS. 7A, B, and C illustrate the derivation of certain basic conceptsof the family of circuits of the invention;

FIGS. 8A and B, and 9A, B, and C illustrate the development of higherorder embodiments of the family of circuits;

FIG. 10 is a mirror image diagram of a specific shift register of thetype indicated in FIG. 9C;

FIG. 11 is a partial mirror diagram illustrating an aspect of theoperation of the circuit of FIG. 10; and

FIGS. 12A, B, and C illustrate the development of a modified form of thecircuit of FIG. 9C.

Three-phase network with toroidal cores The schematic diagram of FIG. 1illustrates two complete stages of the information transfer circuits foran all-magnetic shift register embodying the invention. Each stageincludes six toroidal magnetic cores having a rectangular hysteresischaracteristics defining two stable conditions of magnetic remanence.Information storing cores are designated a and coupling cores aredesignated b. Subscripts on the letter designations indicate theposition of the core in the tandem sequence of shift register sections.

Each shift register section includes a storage core a andelectromagnetic coupling means comprising input and output couplingcores b which are linked together and to the storage core by a loopcircuit L. Each of the cores b is common to two circuits and has aprimary and a secondary portion to which such circuits are coupled,respectively. A full stage of the shift register illustrated includesthree sections of the type just described, but for convenience indescribing operation of the register the stages are divided as indicatedin FIG. 1 at an intermediate circuit plane in every third section. Inputinformation signals from a source 14 are applied at terminals 10 and 11and output is taken at terminals 12 and 13.

Within each section the circuit loop L links the storing cores and thecoupling cores in opposite senses so that a loop current which tends todrive a storing core to one of its stable magnetic conditions also tendsto drive the coupling cores to the other stable magnetic condition. Inaddition, the loop circuits of successive shift register sections linktheir respective storing cores a in alternate opposite directions sothat clockwise currents in all of the loop circuits tend to establishclockwise magnetization in storing cores of odd numbered shift registersections and counterclockwise magnetization in storing cores of evennumbered sections.

Each coupling core engaging two successive loop circuits in the shiftregister is provided with secondary winding turns in larger number thanturns in the primary winding thereof in order to generate gain neededfor overcoming circuit losses. This gain arrangement is convenient whentoroidal cores are employed, but other convenient arrangements forovercoming circuit losses could also be employed.

Cores a and b in FIG. 1 advantageously have approximately the samemagnetic path cross-sectional area, but the cores a have a much longermagnetic path length than do cores b so that the cores a require alarger magnetomotive force when both a and b cores are made of the samematerial. Thus, the a cores require a much larger net current forswitching between stable conditions than do the b cores. As will bedescribed subsequently in greater detail, the cores switch instoring-coupling core pairs when information is being shifted throughthe register. Since the larger storage core and the smaller couplingcore of a switching pair are coupled together by an essentiallyresistanceless loop circuit, they switch at the same rate and developsubstantially equal induced potentials in the circuits coupled thereto.However, drive windings are placed on a and b cores with drive turnsproportioned to provide larger magnetomotive forces to the larger cores,as will be hereinafter described, tg generate a Het 19W current ofpredictable direction. Devices with different path lengths are utilizedin order to have optimum speed and safety margins as is well known inthe art. In FIG. l the'y storing cores a have longer path lengths thando the coupling cores b but the same effect could be produced by othermeans such as by using core materials with different coerciverequirements.

In the circuit of FIG. 1, a practical difference in coercive force forthe cores of a storing-coupling core pair is for the storing core forceto be three to five times as large as `the coupling core force. However,much larger difference factors could be used before any significantdifficulty is encountered as a result of spurious signals generated inshuttled cores that have imperfect rectangularity in their hysteresischaracteristics.

The shift register shown in FIG. 1 is described herein in connectionwith a system of binary representation wherein a bit of binary codedinformation may be either a ONE or a ZERO. Accordingly, in FIG. l it isassumed that cores magnetized in the clockwise direction are set torepresent the binary ONE condition while cores magnetized in thecountrclockwise direction are reset and represent the binary ZEROcondition. The first one-bit stage in FIG. 1 includes a ONE as indicatedby the clockwise magnetization arrows on cores a1, b2, and a2. All othercores are magnetized in the counterclockwise direction.

In FIG. 2 the conventional mirror symbology is employed to depict theinformation transfer circuits of FIG. 1 as well as shift signal circuitsand bias circuits that can be employed with the shift register. Thedetails of a stage of the shift register with all of the aforementionedcircuits being shown, and including winding directions, may be found inFIG. 5. In FIG. 2 the heavy vertical lines represent the magnetic coresof FIG. 1 and bear the same reference characters. The lighter linescrossing these cores represent circuit leads electromagneticallyengaging the cores where short diagonal lines at intersections of leadlines and core lines are provided to indicate lead winding polarity onthe core. Given a direction of electric current flow in a lead, thedirection of flux generated in an associated magnetic core is indicatedby .the direction in which the current direction arrow would bereflected along the core if the short diagonal line at the intersectionis considered to be a mirror. The direction of current induced in a leadby a changing magnetic ux in the core during a ux reversal is indica-tedby following the new flux direction arrow to the end of the core andreturning back along the core in the reverse direction. Now, thedirection in which the reversed iiux arrow is reflected along thelead-in question by the short diagonal line which is considered to be amirror yields the direction of the induced current in the lead.

In FIG. 2 a multiphase shift signal control source 15' supplies signals,of the type illustrated in FIG. 4A, to shift circuits S1, S2, and S3.Source 15 may include any suitable structure such as, for example, anoscillator driving a ring counter having different outputs connected tothe mentioned shift circuits. Circuits S1, S2, and S3 couple the shiftsignals with any required wave shaping and impedance transformation toshift register cores and are considered to include circuit leads linkingsuch cores as illustrated. Details of source 1S and circuits S1, S2, andS3 are not shown because such details do not comprise a part of theinvention.

Shift circuit S1 supplies `shift current pulses from source 15 to coresa1 and b2 with a polarity and sufficient magnitude to reset the coresand generate downward fiux in the core representations of FIG. 2. Thisdownward iiux represents the ZERO binary condition and corresponds tothe counterclockwise uX direction in the cores of FIG. 1. Conversely, anupward iiux in the core representation of FIG. 2 represents a binaryONE.

In a similar manner shift circuit S2 supplies shift signals to cores a2and b3 with a direction and magnitude to reset those cores, and shiftcircuit S3 supplies resetting shift pulses to cores a3 and b4. Sections4, 5, and 6 of the shift register also receive shift pulses fromadditional circuits S1 through S3, respectively, in lthe manner justdescribed with respect to sections 1, 2, and 3. If additional shiftregister stages are provided they would also be supplied with shiftsignals from further circuits S1 through S3 in like manner, because theshift register is characterized by phase symmetry. That is, thecircuitry of each phase position is the same as every other one. In theillustrated three-phase arrangement the circuitry includes a pluralityof circuit nodes numbered in the sequence in which an information frontmoves through the storage cores of the register. Connected to each nodeare two branch circuits to which are coupled a correspondinglysubscripted storage core and coupling core, respectively. Such branchcircuits are included in series in the correspondingly subscripted loopcircuit of the mentioned node. A node and the correspondingly designatedstorage and coupling cores comprise a phase position in multiphasecircuits of the type considered herein regardless of the number ofphases. FIG. 4A illustrates a typical timing diagram of the shift pulsesprovided in a three-phase circuit with each pulse occupying one-third ofthe time slot for a cycle of operation.

Loop circuits for the sections of the shift register are indicated inFIG. 2 by horizontal lines L1 through L6. Those horizontal linesrepresent schematically the correspondingly designated closed loopcircuits of FIG. l. The appearance of double diagonal lines at theintersections of the b cores with certain of the loop circuitrepresentations indicate a larger number of circuit turns on thosecores, than are provided on cores with only single diagonal lines.

Also shown in FIG. 2 are pulse bias circuits B1, B2, and B3 forsupplying bias pulses tending to set the two storing cores, and theirintermediate coupling core, which follow in the tandem shift registersequence a storing-andcoupling core pair which are at the same timereceiving a shift pulse. A multiphase bias signal control source similarto source 15, supplies signals to circuits B1, B2, and B3, which in turnare similar to shift circuits S1, S2, and S3. In some applicationssources 15 and 15 may be a single source.

The pulse bias circuits couple to their respective cores the signalsshown in FIG. 4B. The bias signals occur at the same time as the shiftsignals but are of smaller amplitude because they are not capable ofproducing a switch action without assistance. The bias facilitates thetransfer of information through the register in a manner which will besubsequently described. Also shown in FIG. 2 by a broken lead is adirect-current bias circuit B(D-C) which may be used in place of thepulse bias to bias all of the shift register cores toward the setcondition. The alternative direct-current bias simplifies the biascircuitry, but it requires larger shift pulses to control shift registeroperation. The magnitude of the bias provided either by the pulse biascircuits or by the alternative direct-current bias circuit is such thatthe cores receiving such bias have generated therein a magnetic fieldwhich is somewhat smaller than the coercive field required to switch thedevice from the ZERO to the ONE condition; and extra bias circuitwinding turns are provided on large cores where a single lead links bothlarge and small cores.

FIG. 3 is an arrow diagram indicating conditions of the various shiftregister cores during a complete cycle of three-phase operation for theshift register in FIG. 2. Arrows in FIG. 3` which are directed upwardindicate a ONE condition and those which are directed downward indicatea ZERO condition. Arrows included in FIG. 2 adjacent to the corerepresentations indicate an assumed condition wherein a ONE is stored incores a1, b2, and n2, while all of the remaining illustrated cores arein their ZERO condition. Thus, the arrows of FIG. 2 correspond to thearrows in the top row of FIG. 3 which is designated Initial condition.

A shift current pulse applied to circuit S1 in FIG. 2 drives cores a1and b2 to the ZERO condition, and at the same time pulse bias applied tocores a2, b3, and a3 tends to bias those cores to the ONE condition. Theswitching of cores al and b2 from the ONE to the ZERO conditiongenerates a clockwise current in in loop L1. This current tends to resetcore b1 to the ZERO condition but shuttles that core with no effectsince the core is already in the ZERO condition as will be seen from thesubsequent description of the shift register operation. Since two coresa1 and b2 are switching in loop L1, and induce oppositely polarizedvoltages in loop L1, it is not necessary to provide additional impedancein the loop for absorbing the voltage generated by the switching ofeither of the cores.

The switching of core b2 also produces in loop L2 a clockwise currentim, and this current tends to reset core a2 and set core b3. Theaforementioned setting bias established by circuit B1 in core a2 holdsthat core immune to the effects of loop current 21. However, core b3 isswitched to the ONE condition and generates in loop L3 a furtherclockwise current :'31 which sets core a3 and tends to reset core b4.The setting of core a3 is assisted by the previously mentioned biassignal in bias circuit B1, and this core switches to the ONE condition.Core b4 is already in its ZERO condition and is shuttled by loop current31 without producing an effect in subsequent shift register sections.The forward propagation of the shift signal is thus stopped at core b4.It is because of this blocking effect of core b4, and the similar actionof core b1, previously mentioned, that the coupling cores are sometimesherein designated blocking cores.

Upon the completion of the first phase of the shift operation, thebinary ONE which previously existed in cores a1, b2, and a2 now residesin cores a2, b3, and a3. The switching of cores a1 and b2 from the ONEto the ZERO condition resulted in the switching in the second succeedingloop of the shift register tandem sequence of the cores a3 and b3 fromthe ZERO to the ONE condition. All other cores of the shift registerremain in their initial conditions. The ONE from cores a1 and b2 wasthus leap frogged over core a2 and set into cores b3 and a3. Thecontinuous representation of information by two storage cores and onecoupling core is called symmetry of information disposition.

The second phase of the shift operation is initiated by the applicationof a shift pulse to circuit S2 simultaneously with the application of abias signal to bias circuit B2. The shift pulse switches cores a2 and b3from the ONE to the ZERO condition and the resulting induced currentcauses cores a4 and b4 associated with the second succeeding shiftregister section to switch from their ZERO to their ONE condition in thesame manner previously described for the transfer during shift phaseone. This time core b2, which was reset during the rst shift phase, isshuttled by the counterclockwise loop current in loop L2 resulting fromthe switching of cores a2 and b3 to the ZERO condition. Core b2 thusprevents reverse propagation of the signals. Similarly, core b5 isshuttled by the counterclockwise current induced in loop L4 forswitching core a4 to the ONE condition and thereby prevents unlimitedforward propagation of the signals in the register. Upon completion ofthe second phase of the shift operation, the binary ONE resides in coresa3, b4, and a4. This time core a3 acted as the anchor core when binaryinformation was leapfrogged from cores a2 and b3 of loop L2 to the coresb4 and a4 of loop L4 in the second succeeding shift register section.

During a third phase of the shift operation, core a4 serves as theanchor storing core, and the binary ONE is leapfrogged from cores a3 andb4 of register section 3 to cores b5 and a5 of register section 5 in thesame manner previously described for shift yduring phases one and two.Upon the completion of phase three, and assuming that no additionalinformation is shifted into the cores of loop circuit L1, all six coresof the rst stage in the shift register are in the ZERO condition. Coresa4, b5, and a are in the ONE condition in the second stage of the shiftregister; and cores be, as, and b, are in the ZERO condition.

FIG. 5 shows the manner in which shift and bias connections may beapplied to the cores of the first, or bit l, stage in the shift registerof FIG. l. In this case the coupling lead portions of shift circuits S1through S3 are shown engaging their respective cores with a Windingdirection such that the shift signals of the indicated polarity tend toeestablish counterclockwise magnetization in those cores. Direct-currentbias, of the type shown by broken lines BtD-C) in FIG. 2, is illustratedin FIG. 5 and includes a battery 16 with one terminal grounded and theother terminal connected through a choke coil 18 to a lead 17 which islaced through all cores of the stage and returns to ground. Coil 18presents a high impedance in the bias circuit to switching currentsinduced in lead 17 during core switching. The direction of lacing forlead 17 is such as to establish a bias field in each core in the ONEdirection, and the bias field magnitude is somewhat smaller than thecoercive eld required for switching. In this connection the lead 17 isprovided with a larger number of turns on the a cores than it has on theb cores in order that the single current level in lead 17 may bias allof the cores near their coercive switching levels even though the coreshave different magnetic path lengths.

It may be noted here that input signals to the information circuit ofFIG. l can be applied conveniently at terminals and 11 during shiftphases two and three. During shift phase two a potential difference isapplied at terminals 10 and 11 to drive a clockwise current through loopL0 for driving core b1 to the ONE condition and at the same timeinducing in loop L1 a clockwise current which also sets core al in theONE condition. During phase three the potential at input terminals 10and 11 drives a counterclockwise current through loop L0 therebyresetting core b1 and driving cores b2 and a2 into the ONE condition.Alternatively write-in can be accomplished by a winding linking coresa1, b2, and a2 for switching all three simultaneously to the ONE stateduring phase three.

The write-in operations just described do not conflict with the normalshift operations previously described because of the aforementioned-buffering action of coupling cores. For example, during shift phase onecore b2 was reset and is shuttled by currents in loop L2 during thesecond shift phase as has been previously described. Ilowever, duringthe shift phase two in the two-phase Write-in operation, when cores b1and a1 are being set, the clockwise current in loop L1 also shuttlescore b2 so that the effects of the write-in operation and the effects ofthe shifting operation in phase two cannot interfere with one another.In a similar manner core b3 acts as a buffer during shift phase threewhen the write-in is being completed by the setting of cores b2 and a2.

T hree-phase network with multiaperture devices In FIG. 6 thethree-phase shift register concept is applied to multiaperture magneticdevices. In this case twoaperture devices are employed, and three suchdevices 19, 20, and 21 are utilized to form a complete stage of athree-phase all-magnetic shift register corresponding to that of FIG. 5.Each device includesl magnetic circuit branches corresponding to thecores of the shift register stage in FIG. 5, and corresponding referencecharacters are employed. Thus, each of the magnetic devices in FIG. 6includes a long magnetic circuit branch A and a short magnetic circuitbranch B connected between the ends of branch A. In addition, eachdevice includes a second short branch B which is also connected betweenthe ends of the branch A. The device thus detines a large aperture and asmall aperture. This device may otherwise be considered to include amagnetic core defined by the ybranches B and B' with a further magneticbranch extending between two points on such core. The cross-sectionalarea of the magnetic path in the long branch A is twice the area of themagnetic path cross section in each of the short paths B and B' asindicated by the dimensions 2d and d on the drawing.

Each device in FIG. 6 is in its blocked, or ZERO, state when all of theflux in all of the branches is poled in the counterclockwise directionaround the large aperture las indicated in the device of section 3. Thedevice is in its ONE condition when branches B and B are magnetized inthe clockwise direction around the small aperture, with the innerportion of a large `branch A -being magnetized in the clockwisedirection around the large aperture, and the outer portion in thecounterclockwise direction so that the inner and outer iiux paths oflarge branch A cooperate to form a closed magnetic flux loop. Anintermediate condition, illustrated lby device 20, has counterclockwisetluX around the small aperture with the oppositely poled flux portionsin branch A unchanged from the condition shown for device 19. This alsomay be considered to be a ONE condition since branch A is the storagedevice while the B and B branches are parts of the coupling meansbetween branches.

The device is transferred from the ONE condition to the ZERO conditionin a step-step operation by applying successive pulses of oppositepolarity to a winding on the B lbranch for first reversing the directionof magnetization around the small aperture and then switching the entiredevice flux to the counterclockwise direction. Arrows on the variousdevice ybranches in FIG. 6 indicate an assumed initial condition foreach device wherein the device 19 in section 1 is in the binary ONEcondition; the device 20 in section 2 is in the intermediate conditionwherein flux around the small aperture has been reversed; and the device21 is in the ZERO condition. In the operation considered here, the tluxin the outer portions of the bran-ches A is always counterclockwisearound the large aperture. It must be understood, however, that theillustrated magnetization directions afford an aid in the explanation ofthe operation and are not to be considered a conclusion as to thephysics of operation within a device.

Shift circuits are provided as in the toroidal core embodiment of FIGS.2 and 5, but in this case each circuit directly engages only the largebranch of a device. Bias is provided by a battery 16 and a lead 17 whichlinks all of the large apertures in a direction such as to tend toestablish clockwise `magnetization around the lar-ge apertures. Chokecoil 18 is also provided. The size of the bias current is only suicientto generate the tield in branches A which is just short of the fieldrequired to switch magnetization to the clockwise direction in the innerportions of such branches adjacent to the large aperture.

During phase one the current pulse in shift circuit S1 switches theinner portion of branch A to the counterclockwise direction. Theresulting eld appearing at the ends of branch A1 exceeds the coerciveeld for branch B2 and reverses the polarity of magnetization therein sothat the entire device 19 is now magnetized in the counterclockwisedirection around the large aperture. This places the device 19 in theZERO condition. The switching of magnetization polarity in branch B2generates a clockwise loop current in coupling loop C1 which engagesboth branch B2 and branch B2' in device 20.

The clockwise current in coupling loop C1 reverses magnetization inbranch B2' to establish in that branch clockwise magnetization aroundthe small aperture of device 20 (counterclockwise around the largeaperture). Magnetization in branch B3 is also reversed so that clockwisemagnetization now prevails around the small aperture of device 20. Nochange takes place in the magnetization of branch A2 because anytendency to the inner portion thereof to reverse to the counterclockwisedirection when small branch B2' reverses is opposed @by the'bias fieldgenerated by current in bias lead 17.

The switching of branch B3 generates a counterclockwise current incoupling loop C2 which links branch B3 in device 20 and branch B3 ofdevice 21. The counterclockwise current reverses the :magnetization ofbranch B3 to establish counterclockwise magnetization therein around thesmall aperture of device 21 (clockwise around the large aperture). Sincebranch B4 is already in the counterclockwise direction around the smallaperture it does not change as a result of the switching of branch B3.However, the inner portion of branch A3 does switch to the clockwisedirection around the large aperture of device 21 thereby providing s.closed flux path for the flux in branch A3.

It will be noted that during the lirst phase of shift operation in thecircuit of FIG. 6 there was no flux reversal in branch B1' of device 19or in branch B4 of device 21, and there are therefore no currentsinduced in the input and output circuits for the illustrated shiftregister stage. Thus, the propagation of signals is confined within thethree sections of the illustrated shift register stage as desired. It isalso noted that during the rst phase the ONE condition of branch A1 isleapfrogged over the anchor branch A2 and established in the branch A3.

During the second shift phase the current pulse in shift circuit S2reverses magnetization polarity in the inner portion of branch A2 toestablish counterclockwise magnetization around the large aperture ofdevice 20. This action also reverses the magnetization in branch B3 asecond time thereby establishing device 20' in the ZERO condition sincebranch B2 had been magnetized during the ,first phase in thecounterclockwise direction around the large aperture (clockwise aroundthe small aperture). The second reversal of -llux in branch B3 generatesa clockwise current in coupling loop C2 which causes branch B3 to bereversed again. This action causes magnetization of branch B4 toreverse, thereby completing clockwise magnetization around the smallaperture of device 21 and generating a counterclockwise current in theoutput coupling loop from the circuit of FIG. 6i.

During the third phase of the shift operation, the shift current pulsein circuit S3 reverses magnetization in the inner portion of branch A3thereby producing a further reversal in branch B4 for establishing indevice 21 the complete counterclockwise magnetization which ischaracteristic of the ZERO condition and generating a clockwise currentpulse in the output circuit loop. All three sections of the stage inFIG. 6 are now in the ZERO condition if no write-in signals have beenapplied to the input circuit. If, however, write-in signals have beenapplied they would appear as a counterclockwise loop current in theinput circuit during phase two and a clockwise loop current in the inputcircuit during phase three.

Improving speed and operating margins The three-phase shift registerembodiments hereinbefore described utilize different core sizes and biascircuits to help control spurious switching of cores that must beshuttled by switching currents but which are not supposed to switch eventhough the shuttle current may be in a direction tending to causeswitching. Mutual couplings with step-up turns ratios are used to obtainthe gain necessary to overcome losses, but the arrangement of turnsratios is relatively simple because of the relatively simple couplingarrangement between register sections.

The possibility of spurious switching of shuttled devices in thedescribed register can be considerably reduced by providing additionalstorage devices, with an increase in the number of shift phases, in theregister so that drive currents from a transmitting storage device to areceiving storage device are, in the current return path, split amongmultiple circuit paths. However, increasing the register phasesincreases the complexity of the interplay among couplings betweenregister sections so that such register systems, and their benelits, aregenerally avoided by designers. In accordance with the presentiiivention, it has been found that the three-phase register of FIG. 2herein is the lowest phase order embodiment of a family of registershaving other higher phase order embodiments, and wherein the marginagainst spurious operation increases with increase in the phase order.

All of the member registers of different phase orders in theaforementioned family are readily derivable by a logical equivalentcircuit type of approach. Once a certain phase order embodiment has beenderived, different modifications thereof can be formulated to achievemaximum manufacturing convenience for different situations. Theequivalent circuit representation for any given phase order register isalso the basic information transmission circuit for such a register ifit employs bipolar magnetic devices, e.g., anisotropic magnetic thinfilms, having inherent gain. For unipolar devices, e.g., toroidal cores,the basic equivalent circuit must be modified to insert gain-producingmeans; but in accordance with the present invention a relativelyeasy-to-follow procedure is available for determining how to produce theneeded gain by turns ratios and/ or magnetic path-length arrangements.Consequently, the use of higher phase order circuits to achieve desiredmargin is more conveniently available. The procedure for deriving thementioned equivalent circuits and for adding turns ratios when requiredis hereinafter outlined. The discussion will be developed in terms ofunipolar toroidal cores; but other types of devices, either unipolar orbipolar, can be employed.

It has been found that in a shift register maximum energy gain and speedof operation over plural phase positions are available when the registeris characterized by substantially identical energy gain and speed ofoperation for each phase position thereof. Consequently, it is desirablethat each phase position of the register should be identical to everyother and that any operation accomplished on one phase position shouldlikewise be subsequently carried out on every other phase position. Thismeans, of course, that registers of the class should have identicalconnection circuits for each phase position in a multiphase arrangement.A plurality of the phase position circuits are combined, as shown forexample in 1, to form a bit storage position, or stage, of a shiftregister. In the absence of interstage storage means each register stagemust be able to transmit and receive information at the same time.

In any shift register it can be shown that the ratio of magneticmaterial volume of receiving cores to material volume of cores in thecurrent return path for a stage of the register determines the gain andthe speed of information transfer between transmitting and receivingstorage cores. Thus, if the ratio is less than unity the return pathcores have the larger total volume and require a correspondingly largertotal magnetomotive force for switching than do the receiving cores.There is then less danger of spuriously switching the information stateof return path cores. The volume ratio also determines the tolerancesassociated with external drive signals applied to the various registercores. If the material volume ratio can be decreased, operating speedincreases; but heretofore no practical way was known to achieve such anadvantageous ratio in shift register involving more than a fewinformation transfers.

It is assumed throughout this discussion that the shift register willhave a single transmitting core and a single receiving core. In anm-phase embodiment m distinct storage elements are required, one to actas a receiver and one as a transmitter on each transfer phase, i.e.,during each resetting of a storage device by a shift signal theinformation stored therein is transferred to another device. During agiven transfer phase the m-Z remaining storage elements in a stage arecoupled to transfer current return paths for returning the informationtransfer current from the receiving device back to the transmittingdevice. In the three-phase circuit the leapfrogged storage deviceperformed this function as will hereinafter be further considered.

It can be shown that the shift register circuit of FIGS. 1 and 2conforms to an algorithm for circuit construction utilizing anequivalent circuit approach to optimize signal transfer current. Thus,the three-phase circuit of FIG. 2 has an equivalent primary circuit. Thelatter circuit can be modified by adding additional storage cores anddrive phrases in la way which increases the available transfer currentfrom a transmitting core of the register without significantly changingthe impedance of the receiving stage. Consequently, the material volumeratio of the register is decreased with the result that the gain perstage is increased `and the speed of operation of the register isincreased. This register modification requires additional hardware, butit gives the designer a degree of flexibility that he lacked beforebecause he can now select an advantageous comprise between hardware costand speed of operation.

In accordance with the aforementioned algorithm, an mth phase ordersystem utilizes m drive phases per stage and m storage devices perstage, i.e., per information bit. m-l of the storage devices areactually utilized at any one time for storing information. This leavesone storage device free to function as a receiving device so that eachregister stage may simultaneously transmit to a succeeding stage andreceive from a preceding stage as required for register operation. Theexpansion from the third phase order shift register to a higher phaseorder to gain a decreased volume ratio requires additional seriesinformation transmission paths having storageV cores. Information isshifted along each such path between the first and last, i.e., the(n1-1)m core after the first, cores of a stage in the same path. In eachsuch shift the transmitted information leapfrogs by other cores in thestage in other series paths.

Drive signals are successively applied in different phases to thestorage cores of a stage in a rotating sequence of the series paths. Forexample, referring to FIG. 1, lthe third phase order shift registerthere illustrated employs three storage cores per bit and three drivephases, i.e., m=3 for the register of FIG. l. Consequently, m-l--Z forthe shift register of FIG. 1 so that two storage cores are actually usedto store an information bit at any one time. Likewise, two seriesinformation transmission paths are provided in that register.` The firstsuch path includes the odd numbered loop circuits L1, L3, et cetera, andthe second path includes the even numbered loop circuits L0, L2, etcetera. Thus, within a stage of the register the shift signals aresuccessively applied to those first and second paths in rotatingsequence as cores al, a2, and a3 are driven in succession.

Further in accordance with the aforementioned algorithm, the addition ofseries information transmission paths is equivalent to the addition ofmultiple return current paths equal in number to m-2 and which share atotal information transfer current. The equivalence will now beconsidered.

Developing a primary network Development of higher-phase order circuitsis first considered in a skeletal, or so-called primary, network form inwhich two turns ratios are included. YIdeally a circuit would operate inthis equivalent circuit form if there were no resistance or flux losses.This circuit form is simply derived from FIG. 1 by:

(a) Considering n (turns) equal to one on all blocking cores as shown inFIG. 7A.

(b) Primary and secondary windings are now unnecessary on blocking coresexcept in regard to electrically isolating one loop from another.However, it can be seen that there is no electrical potential differencebetween adjacent loops so that isolating action is unnecessary.Therefore, primary and secondary windings can be combined into onecircuit, thereby directly joining node points such as 222 and 3"33 inthe various loops as seen in FIG.

12 7A. This produces the primary network as shown in FIG. 7B.

The information ONE bit is shown in the circuits of FIGS. 7A and 7B thesame as in FIG. 1. The operation of the primary network of FIG. 7B,neglecting losses, is essentially the same as that discussed for FIG. l.This similarity can be seen in the following outline description. If thedrive winding S1 in FIG. 7B is energized as shown in FIG. 7C, the ONEinformation states of elements al and b2 are reset, and equal voltagesem and ew are induced across nodes 1 and 3 and nodes 2 and 3,respectively, as shown in FIG. 7C. Drive magnetomotive forces areadjusted by seiecting differing turns on shift windings S1 for cores aland b2 so that core a1 tends to switch slightly faster than does coreb2. Then the net loop current el in loop L1 is clockwise so that elementb1 in the clear state is shuttled and acts essentially to short node 1to node 2. This latter action stops reverse propagation at nodes 1 and2. The voltage @b2 causes a clockwise current :'62 around loop L2,switching element b3, which in turn causes a clockwise loop current :'83in loop L3. The latter effects switching in the receiver storage elementa3 and blocking action, or shuttling, in element, b4. So forwardpropagation is stopped at nodes 4 and S.

Note that with no losses, as previously assumed, the total flux switchedin setting elements 13 and b3 must be equal to the ux switched inresetting elements al and b2. However, it is clear in FIG. 7C that thereturn current path for the switching branch currents ias and iba isthrough element a2 and in a direction to cause switching toward thereset state in this element. The principles of conservation of energydictate that any such spurious reset switching in core a2 will reduceenergy available to the receiving cores, i.e., reduce the signal fiuxpb3 and rpaa that can be switched. Thus, a partial loss of informationwould occur, and this effect must be avoided. The bias magnetomotveforces which aid switching to the set condition in cores b3 and a3 andprevent switching to reset in cores a2, as discussed in connection withFIGS. 2 and 5, also assist in avoiding the spurious switching. Inaddition, it is necessary in the circuits of FIGS. 2, 5, and 7C toadjust the magnitude of drive signals S1 so that the sum of iaa-t-bg isnot greater than the biased threshold of element a2. Hence, the coerciveforce threshold of a core coupled to a return current path willact tolimit the maximum usable transfer current for each shift phase. In otherwords, the power transfer per phase is limited by the total magnetictheshold of the drive current return path. The object of the subsequentdiscussion herein is to show how this limit can be increased byproviding multiple current return paths through elements storinginformation such as the core element a2.

The drive, or transfer, current return path is clearly `identifiable assuch in FIGS. 7B and 7C which are completely direct-current coupled. Anequivalent return current branch circuit is included in the circuits ofFIG. 7A and in FIG. 1 which have inductively coupled loops. For example,in FIG. 1 the loop current im causes core b3 to be switched as alreadydescribed; and it also causes, by coupling through core b3, the core a3to be switched. It can be shown by known circuit analysis techniques,therefore, that the loop current 1'21 in FIG. l corresponds to thecurrent :g3-Hhs in FIG. 7C, and that the circuits of cores a2 in bothcases comprise return current paths which are equivalent to one anotherfor the information transfer operation. Accordingly, current returnpaths are hereinafter considered to include intermediate core circuits,such as the circuit of core a2, between a transmitting portion of corecircuits that are driven to generate an information transfer signal anda receiving portion of core circuits that are actuated in accordancewith the information significance of such transfer signal, regardless ofwhether such return paths are in a direct-current coupled network as inFIG. 7C or in an inductively coupled net- 13 work as in FIG. 7A andregardless of the number of operating phases used for the over-allcircuit.

Note in FIG. 7C that after the first transfer phase the disposition ofinformation-indicating flux is in exactly the same pattern astheretofore but displaced to the right by one phase position. That is,information now lies in elements a2, b3, and a3 instead of a1, b2, anda2. The second transfer phase drive signal S2 can now be applied toeffect another such shift and the third drive S3 after that. During eachtransfer phase, the pattern of functions being performed by storage andblocking cores in each bit position is the same. For example, duringdrive S1 in FIG. 7C, blocking cores b1 and b4 at the inputs to adjacentbit positions serve to isolate transfer currents to the associated setof transmitting and receiving core loops. One storage element a1 and aninternal blocking element b2 are used as transmitters in a bit positionwhile another storage element a3 and an internal blocking element b3 actas receivers in the same bit position. The remaining storage element a2acts as the limiting, transfer current, return path.

The functions of the various cores change cyclically as information isshifted through the register so that bit positions are not structurallydefined in a fixed manner as they are in many prior art registers.However, the phase position structure is defined and is utilized tobuild up multiphase netwoks comprising a register of t-he desiredlength. The register is built up in iterative fashion on a node by nodebasis. Each phase position includes a node with one storage element andone blocking element coupled to separate branches from the node. Thegenerating rules for connecting these elements in the three-phasecircuit are as follows:

Rule (a) Each storage element al directly joins a node z' to a nodei-l-Z.

Rule (b) Each blocking element b1 node i to a node i+1.

The primary circuit, eg., FIG. 7C, formed by these rules represents asymmetric class of circuits in that the circuitry of each phase positionis exactly the same as all the others.

directly joins the Development of networks of dz'erent phase orders Theprimary networks of higher phase order registers of the mentioned classof phase-symmetric registers can be obtained by extending theaforementioned generating rules to include the general phase orderfactor m. To this end the significance of phase order in thethree-phase, i.e., m=3, network must first be considered. In one bitposition, i.e., bit 1 of FIG. 7A, it is seen that there are m storageelements, m blocking elements and m nodes. The last numbered node in thebit position, or node z`|mt1 for a position beginning at node i, acts asthe single internal node connecting transmitting and receiving elements.The remaining m-l nodes all appear as input nodes for current from aprevious bit position.

Since in the higher phase order schemes one still wishes Vto activateonly a single transmitting element and a single receiving element, theclose transmitter-to-receiver coupling of the three-phase circuits isretained in circuits of higher phase orders. In other words,intermediate storage between transmitting cores and receiving cores isplaced in the return current path for transfer current rather than int-he forward coupling path. Rule (a) is then restated as:

Each storage element including a core ai directly joins node z' and nodei-i-m-l.

Since the register is to be symmetric this rule serves to define thelocation of all storage elements utilized in the phase positions neededfor a register of the desired length. A full bit position includes msuch storage elements.

The primary function of the blocking element b1 will remain the same asin the three-phase example, i.e., to shuttle, or in effect shortcircuit, input node points of 14 bit positions during a transfer. Thus,Rule (b) is the same as before:

Each blocking element bi directly joins the node i and node i+1.

The complete primary information transfer network is derived as shown inFIG. 8A for 111:4.

In FIG. 8A, which has been extended so as to store ltwo full bits ofinformation (nodes l to 8), a ONE signal has been shown in the first bitposition. The disposition of signal-representing ux states for a ONE canbe determined from the three-phase example. In general m-l successivestorage elements are left storing a ONE while the mth element is leftfree to act as a receiver. If the :first bit storage location is ai thenblocking elements bi to bi+m3, inclusive, are left clear to preventreverse propagation in the m 3 version. Blocking element bi+m 2 is inthe ONE condition and is used together with storage element ai as atransmitter on a particular phase while blocking element b+m 2 is leftclear to act as a receiver with storage element ai+m 1.

The characteristic signal transfer opeartion in one phase of afour-phase system, but which is identical for all phases, is hereindescribed with reference to FIGS. 8A and 8B. Drive S1 is applied toelements a1 and b3 in the first bit position as shown in FIG. 8A. -It isalso applied, but not shown, to elements a5 and bq in the second bitposition, and it is similarly applied to corresponding cores in otherbit positions. Equal induced voltages eal and @1,3 act in parallel, asindicated by dotted arrows in FIG. 8B. Elements b1 and b2 which blocksignal propagation to the left act as shuttled or short circuit paths.Elements a4 and b4 switch with voltage em impressed across theirterminals. No switching occurs in element bs due to the direction ofreceiver current as shown. Similarly, elements b1, b2, and b5 are merelyshuttled by a portion of the receiver current a4. Core a4 requires amuch larger current for switching than does core b4. Consequently, thecurrent ia4 is much larger than the current im; and it controls thecondition of core b5.

The total receiver current a4-i-z'b4 in FIG. 8B on shift signal S1 isapproximately evenly split between the two current return paths throughelements a2 and a3. Thus, with these two paths the .transfer currentupper limit, below which no spurious switching of information occurs incores a2 and a3, is doubled over that in the three-phase example. Notealso that since elements b5 and bf,- are blocked while information isbeing shifted from a1 to a., by shift signal, S1, a 'ONE or ZERO cansimultaneously be shifted in the same manner from element a5 to a3 byshift signal S1. In other words, bit transmissions in adjacent bitpositions are isolated from one another by the iblocking elements b5 andbs. Furthermore, because of the phase symmetry of the circuit, cores b5and be are also shuttled by the return current :'5 of core a5 in thenext bit position if it were storing a ONE prior to the drive phasesignal S1.

At the conclusion of the tarnsfer operation just outlined, the ONEsignal flux has been moved to elements a2, a3, a4, and b4 from itsoriginal position in a1, a2, a3, and b3, i.e., to a position with allnode numberings incremented by one. Thus, if no flux has been lost inthe process, the next shift operation can be performed exactly as thefirst but with drive -winding S2 (linking elements a2 and b4) energizedas shown in FIG. 8B. Two further such shifts are then required to movethe information through the remainder of a complete bit position. It canbe seen by analogy to the discussion of the three-phase circuit that thefour-phase circut includes three information transmission paths and thatwithin a bit position in the register the shift signals are applied tothe storage devices of the different paths in rotating sequence. Thefirst path includes nodes 1, 4, 7, and 10; the second path includesnodes 2, 5', and 8; and the third path includes nodes 3, 6, and 9. Theapplication of shift signals in the position for bit 1 is to the threepaths in the rotatiig sequence represented by cores a1, a2 a3, and` a4.

The derivation of networks of higher phase order than the fourth followsdirectly from the method just outlined. Clearly, with five phases threecurrent return paths are available. Thus, each phase transfer can beaccomplished at a higher transfer current level without loss ofinformation flux. Hence, the allowed margin in shift current amplituderange increases. Note that the lower bound on shift currents is the samefor all phase orders since it is the drive which will induce a transfercurrent above the threshold for switching of one storage element and oneblocking element in the receiver section of the register. With higherallowable transfer current levels in circuits with four or more phases,the time required per transfer between cores is reduced with respect tothe three-phase circuit. More transfers are required per bit shift, butnote that in practice it has been found that there is a great deal timesaving in putting b bits through n stages of a higher phase orderregister.

Alternative storage devices In the network derivation included herewith,simple torodal cores of ferrite material have been used for purposes ofillustration. The networks, however, are suitable for various othermagnetic element configurations. -For example, a direct analyticalcorrespondence can be made between the simple core topologies and thoseof networks using multiapertured magnetic elements. Several equivalentmultiapertured arrangements can be shown for one primary network, andone example was discussed in connection with FIG. 6 for the three-phasecircuits. Alternatively, it is known that other magnetic elements of abipolar signal handling nature can be used in substitution for thesimple ferrite cores. With these a flux condition of a rst polarity canbe used to represent a fONE, an oppositely polarized flux conditionrepresents a ZERO, and a neutral or null ux condition represents theno-information state. Transmission of ZERO states occurs in a manneridentical to that described for ONES with all currents, flux, et cetera,reversed in polarity. In bipolar schemes blocking elements generallyrequire a holding field applied externally to prevent them fromswitching. Magnetic thin films, as in the R. M. Wolfe Patent 3,175,185,and balanced bipolar ferrite elements tiled Nov. 30, 1962, now U.S.Patent 3,376,562 which as in the E. E. Newhall application Ser. No.241,339, issued Apr. 2, 1968, and entitled A Magnetic Core ShiftRegister, are two members of the class of such bipolar devices.

Gain inserted as flux increments In discussing the operation of theprimary network examples herein it has been assumed that coupling wiresand magnetic elements, when driven between specified limits, arelossless. In practice this is not the case. The use of ferrite coreelements in a network connected as in the described primary circuitsresults in essentially the same mode of operation although with graduallowering, by each subsequent transfer, of the signal ux level. Whenusing anisotropic film elements this does not occur as it has beendemonstrated that the elements themselves have the ability to regeneratea stable signal ux level as taught in the mentioned Wolfe patent. Withmost other devices, however, multiple windings incorporating turnsratios are employed to provide a net signal ux gain in spite of losses.In addition, it is often found necessary to increase signal energylevels for increasing either magnetic path length or the flux pathcross-sectional area, or both, of the switching elements. The means fordesigning such multiple winding congurations so as to maintain symmetryin multiphase operations is not evident with systems higher than thethird order. The following discussion shows the necessary analyticalprocedures for conveniently adding turns ratios for circuits with anynumber of phases.

From the foregoing discussion of the primary, or direct coupled,networks it can be seen that a given information signal (a ONE signal inthe unipolar element examples of FIGS. 7 and S) must give rise toinduced branch voltages em, for example, appearing in the network atinformation signal transfer times. Furthermore, in a particular transferany branch which is required to switch either to the information stateor back to the clear state must, if lossless conditions prevail, exhibitthe same voltage drop 4as every other branch. In a symmetricallydesigned system in which each transfer occurs at the same rate and forthe same duration, it is further evident that, regardless of the phasetime at which switching occurs, the same voltage waveform should appearacross any branch in the network when that branch is induced to switch.This can be seen for the network of FIG. 8A, where on the rst phase asdescribed, element b3 switches with element a1 thereby requiring equalvoltages between the node pairs 1, 4 and 3, 4. However, due to thesymmetrical drive arrangement, it is also noted that element b3 was setto the ONE state on the phase f previous together with element a3. Thus,eba on this phase (S1) equals ea3 that had been produced on a previousoccurrence of phase S3. Since no flux or integrated voltsecond signal islost between phases it is then clear that:

Consideration of all phases in turn then yields the constraint on thedirect coupled networks of FIG. 8A that all volt-second switchingsignals are equal, i.e.,

llfi=ni p1 (4) Hereinafter the A is dropped and rp, is understood torepresent Aoi. Thus, for all blocking and storage elements in a directcoupled network, the Equations 1 through 4 yield the constraint that:

/j=\1 (5) Clearly if a uniform ux gain per phase n were to be obtainedin each transfer through a long direct coupled network such as that inFIG. 8B:

{9si=77i.i1pai for 97 1} bs=11"bif0rj i, n 1 (6) from Equations 4 and 5this would require an impractical exponential decrease in the numbers ofturns on succeeding elements through a long register:

It has been demonstrated for the three-phase circuit that the longdirect coupled network is equivalent to a similar network of pluralinductively coupled circuit loops. This equivalence provides a practicalalternative to long direct coupled networks with exponentiallydecreasing turns. The alternative is to construct the register with manysmaller, isolated, direct coupled loops and rely on mutual couplingbetween different windings on a coupling core to form a circuitconnection essentially 17 equivalent to that of the direct coupledcircuit. In the case where loops are coupled by mutual inductance,Equation applies to only the flux linkages within any one such directloop. Hence, the various loops for the three-phase circuit can bedesigned separately using Equations 5 and 6. Usually this will be donesymmetrically, i.e., all loops being designed identically, one for eachphase.

The essential factor in selecting a coupling loop is, of course, that itcan be congruent with a loop already present in the primary networksince otherwise a new effective current path not present in the primarycircuit would be established changing the mode of signal transfer. Somepossible coupling loops for a four-phase register are shown by brokenand dotted lines in FIG. 9A. Note that each branch in the loop whichruns parallel to a primary network branch must link the core element inthat branch. In addition, with all phase loops completed, every primarynetwork branch must appear in at least one loop.

To further illustrate the design technique it is convenient to considerthe case where all storage cores in the register are identical in size,shape, and material. Blocking cores are likewise designed to beidentical to one another but different from storage cores as noted forcoupling cores for FIG. 1. A flux gain of v; 1 is to be provided tocounterbalance the unavoidable losses in the register due to sucheffects as signal IR drops and partial spurious switching to give anover-all signal transmission gain of unity through a shift register. Thecongruent loop configuration of FIG. 9B is chosen from those of FIG. 9Asince it appears to link as few cores as possible, i.e., cores a1, b1,b2, and b3; and it will, therefore, involve the lowest number of phasepositions and the lowest j-i spread in exponents for Equation 7. Theentire register will be reformed using identical loops of this type asshown in FIG. 9C. The polarity of linking windings must be chosenconsistently as shown in FIG. 9C where all windings go through the holesin the cores from top to bottom when tracing them from leftmost torightmost ends of the branch.

For reasons earlier discussed, the flux linkage constraint of Equation 5must apply to all elements connected within any one of the shortgenerating loops of FIG. 9C. Further, design Equations 6 again apply toall elements of the same type, either storage or blocking, within theloop. v7, or the flux gain per phase, must be obtained from a priorknowledge of expected losses in wires and cores as is usually the casein design work. Thus, Equations 7 are again obtained specifically forthe loop L1 in FIG. 9C so that:

Turns nal for storage core a1 can be chosen relative to the turns nbg inaccordance with Equation 5 alone, i.e.,

Since equivalent loops are to be used for manufacturing convenience forall phase groupings of elements, the nodal subscripts in Equations 8 and9 can then be replaced with general subscripts i, i+1, et cetera whenconsidering the turns in Loop Li to reect the precession of loopposition in successive phase positions,

To further illustrate this example consider a register designed withstorage cores having a capacity of x units of flux and blocking coreswith a capacity of .75x units 18 of flux. The estimated ux gain requiredper phase is advantageously selected to be 1.5.

Then from Equation 8:

Jaa: nhl

5 W51=Tnb3 (13) Clearly from a manufacturing standpoint it is desirableto have turns values satisfying Equations 12 and 13 which are integral,and the lowest integral values are thus:

"151:9 111,226 nba=4 111:3

A complete register wired with coupling loops of this type is shown withmirror symbols in FIG. 10 including all bias and shift windings. Notethat the shift windings S1 through S4 are placed on the cores asindicated in FIGS. y8A and 8B but with two turns on the storage coresand one turn on the blocking elements. The choice of turns for applyingshift signals is not restricted by flux gain and symmetry constraintsbut was found convenient for manufacture.

At the input of the register of FIG. 10 is shown an information write-incircuit not discussed heretofore. The primary networks shown in FIGS. 8Aand 8B were considered as sections in a long register so that initialinformation patterns given were the assumed result of four previousphase transfers. At the input end of a register a single phase write-inis more convenient, in terms of external pulse equipment for insertingthe desired information pattern, than is a multiphase write-in. This isthe function of the Initial Write-in winding shown in FIG. l0. Clearly,a pulse drive winding linking each of cores a1 a2, a3, and b3 so thatthey could be fully switched by a current pulse would serve thispurpose; however, one would then have to rely on dimensional accuracy ofthe initial elements to insure equal signal storage in all elements. Thewinding shown, which links element a1 with four turns, element b1 withtwo turns, and one turn on element b2, performs the same task but relieson induced loop currents resulting from the switching of element a1 toprovide corresponding signal levels on element a2, a3, and b3.

The path of the FIG. 10 currents induced on write-in is` shown on FIG.1l where it can be noted that the twoturn and one-turn portions of thewrite-in circuit are found sufficient to prevent unwanted switching inelements b1 and b2 due to induced write-in currents. Writein in thismanner is performed during the drive phase when drive signal S4 performsthe added function of holding element a4 in the clear state. A biaswinding, which is advantageously used to enhance the performance of theregister as in the three-phase example, is not shown in FIG. 11 as arethe remaining drive windings which are inactive during write-in. Severalalternative write-in winding arrangements are clearly possible.

Gain by magnetomotive force increments turns levels on circuits as aresometimes required for flux increments only or to allow the use of loworder 19 integral turns levels. For example, if in one circuit loop theturns can be proportioned with only two levels of turns such as 173 and1, rather than the three levels if an n2 level is also needed, then thedesigner is free to use unity for the lower level and any convenientnumber such as two turns for 1,3.

Considering the ease with which turns ratios can be used to provideimpedance matching in magnetic circuits in general, the use ofmagnetomotive force as well as uX gain in a magnetic register isreasonable, and it is often operationally convenient. Safeguards,however, should be taken in the symmetric class of circuits usingmagnetomotive force and flux gain as well as in those using only fluxgain, as previously described, if it is desired to retain the uniformityof transfer phases with regard to factors such as transfer speed andpower transfer.

It can be shown directly that the symmetry requirements are mostconveniently achieved by requiring:

(a) The use of a phase symmetric primary network as previously derived',

(b) The adjustment of drive s and proportioning of turns and linearcircuit parameters (such as leakage inductauce and wire resistance) sothat each core of a given type (either blocking or storage) will beoperated with identical excursions in net eld intensities Hai or Hm, andidentical excursions in signal iiux densities Bai or Bbi; and

(c) The use of identical bulk material and geometric type, but withdifferent dimensions on various devices. Conditions (b) and (c) aloneindicate that identical switching times are obtained in all elementsthroughout the network since switching properties are xed for thematerials in terms of B and H input variations.

For either a blocking or a storage element at the time of write-in,energy requirements are obtained as follows: 810) ="i Pi()=fli-411(f)(14) where ei(t) is the terminal voltage across n, turns on the elementwhen switching,

tpl( t) is the rate of change of flux switching in that element,

U) is the rate of change of (flux density.

Ai is the net cross-sectional area of the core flux path, MMFU) is thenet lmagnetomotive force of the niturn winding with current ,(t)flowing, i.e., niii(t),

I, is the mean magnetic path length of the element, H(t) is the net eldintensity due to ii.

message@ The energy requirement for switching the element is then:

By substituting in the above from Equations 14 and l5:

i-Oifl-iiaitarmudt (16) where -ri is the switching time of the element.Clearly if ,-(t) and H1(t) are the same on all elements of a given type(either blocking or storing), subscripts can be dropped, and theintegral term then can rbe considered a constant K for all elements.Hence:

Aili f Wi 0.43K 17) Since B and H have variations that are the same fromelement to element, the element dimensions Ai and 11 are assigned valuesfor the various elements to be proportional to flux and magnetomotiveforce requirements. Thus:

The signal energy gain between two equivalent locations, e.g., storecores ai and aj, in the register separated in signal receive time by j-iphases is then:

WTMT, (19) For symmetrical operation the total energy gain per phase isa constant v1. Expression l'9 can then be Written:

aMMF, MMF (20) This expression can be seen to be equivalent to Equation6 where MMFJ=MMF. Equation 5 relating flux linkages on elements directlyconnected within one coupling loop must still apply.

This proportioning of turns ratios, element cross sections, and pathlengths can proceed under the restraint of Equations 20, 4, and 5 once avalue of n and a generating, or coupling, loop conguration have beendecided upon by the designer.

The procedure, for example, can be performed as follows, consideringagain the four-phase register of FIG. 8A using generating loops as inFIG. 9B. The cores and primary network are irst drawn out as shown inFIG. 12A and desired flux and MMF levels, in accordance with Equation20, are assigned. Note that p and MMF levels in the blocking and storingcores are assigned using Equation 20. Blocking core levels are assignedindependently of the levels in the storage cores except insofar asEquation 5 is concerned. Thus, let the levels in core a1 be (px andMMF,C while in blocking core b1 the levels are py and MMFy. These aredetermined, as is known in the art, by the designer from a knowledge otswitching and threshold properties of core types which are known to besuitable for particular types of applications. Equation 20 then servesto restrict the designers choice of all remaining core variable levelsin the register.

In the example of FIG. 12A the design object has been to utilize lMMFgain alone on alternate phase positions, i.e., on phases 2, 4, etcetera, and on intermediate phases the phase-to-phase gain is achieved-by circuit turns. In addition, at the intermediate phase positions thepath length gain in the preceding phase position is transferred to fluxlevel gain by circuit turns and MMF level drops back to correspond tothe original path length. For the elements a2 and b2 of the second phaseposition, from Equation 20:

The proposed coupling loops are now figuratively placed on the coreswith turns adjusted in each separate loop to satisfy Equations 4 and 5with respect to the assigned linx levels. This is shown in FIG. 12Bwhere 172 represents the number of turns in terms of gain per phase.

2l Although the wires are drawn with single-turn linkages, thealphameric indications show the actual numbers of turns. The polarity ofwindings, of course, must agree with that shown as a single turn.

Around lopp L1 in FIG. 12B flux and turns levels are thus:

The equality of oy and ox is selected for manufacturing convenience andrequires flux paths to have equal crosssectional areas.

Each loop is thus designed until a repeating pattern is established,i.e., odd numbered loops are the same as loop L1 and even numbered loopsare the same as loop L2. Note that the only turns levels employed are112 and l so that no difficulty in applying integral values isexperienced with this design It may further be noted in FIG. 12B that inthe blocking cores at least two windings appear with identical numbersof turns so that these may be combined in one winding as in the originaldirect coupled primary network. Thus, the equivalent couplingarrangement of FIG. 12C is obtained with winding turns as shown.

The foregoing has been intended to show some of the variations possiblewith one member of this family of circuits. Clearly the analyticaltechniques described can be further applied to fit the register to avariety of applications. Basically, however, the mode of operation, thesequence of element switching, and performance of all such equivalentcircuits will be the same as described for the primary network.

Although this invention has been described in connection with particulararrangements and applications thereof, it is to be understood that theseare merely for the purpose of illustrating the underlying inventiveprinciples; and additional applications and embodiments which will beobvious to those skilled in the art are included within the spirit andscope of the invention.

What is claimed is:

1. An all-magnetic logic network comprising a magnetic storage devicehaving set and reset stable states of magnetic remanence,electromagnetic coupling means having input and output portions, eachportion being operatively coupled to the other and to said storagedevice in opposite senses, each of said portions having a set state anda reset state of magnetic remanence,

means applying input signals to said input portion for switching suchportion back and forth between its set and reset states for setting saidstorage device upon switching to the set state and for setting saidoutput portion upon switching to the reset state to generate an outputsignal of a first polarity, and

means applying a control signal to said network for simultaneouslyresetting said storage device and said output portion for generating anoutput signal of a second polarity.

2. The logic network of claim 1 in which said storage device is atoroidal magnetic core,

said coupling means comprises further toroidal cores as said input andoutput portions, respectively, and an electric loop circuit linking saidstorage core in one sense and linking both of said input and outputcores in a sense which is opposite to the sense of the linking in saidstorage core, and

said control signal applying means is a circuit lead for conductingcurrent through said storage and output cores in the same sense.

3. A shaft register comprising a plurality of sections each including astoring magnetic core and coupling cores, each of said cores having asubstantially rectangular hysteresis characteristic defining two stableconditions of magnetic remanence, and a coupling loop circuit linkingsaid storing core with two of said coupling cores, one being an inputcoupling core and one being an output coupling core, the output couplingcore of each loop being also the input coupling core of the loop in thenext succeeding section of the shift register,

a source of shift signals including means successively applying shiftpulses to said storing and output coupling cores of each section insuccession for driving such cores to a rst one of said two conditions,and

means biasing to the second one of said stable conditions the storingcore and input coupling core of the second section following a sectionwhich is receiving a shift signal.

4. An all-magnetic shift register comprising a plurality of magneticstorage devices having set and reset stable states of magneticremanence,

electromagnetic coupling means having input and output portions with setand reset states of stable magnetic remanence coupling said devices in atandem sequence of shift register sections with one of said devices ineach section, each input and output portion of each section beingoperatively coupled to the other in one sense and coupled to the storagedevice of the section in the opposite sense, the output portion of eachsection in said sequence being operatively coupled to the input portionof a following section for switching such portions in step to the samestates,

means applying input signals to said input portion of the first sectionof said sequence for switching such portion back and forth between itsset and reset states for setting the section storage device uponswitching to the set state and for setting the section output portionupon switching to the reset state, and

means applying control signals in time controlled order to the sectionsin said Sequence for, in each section, simultaneously resetting thestorage device and the output portion of such section.

5. The shift register in accordance with claim 4 in which said inputsignal applying means are operative during times when no control signalsare being applied to said first section.

`6. The shift register in accordance with claim 4 in which said sectionsare arranged in said sequence in a plurality of groups of m sectionseach, and

said control signal applying means comprises m electric circuitssupplying control signals to said m circuits within each group indifferent phases, respectively, a total time T being required forcompleting a cycle of said different phases, and the time during whicheach phase is supplied being T/m.

7. The shift circuit in accordance with claim 4 wherein means supplybias signals generating magnetomotive forces of proper polarity butinsufficient magnitude to switch said devices to their set conditions.

S. The shift register circuit in accordance with claim 7 wherein saidbias supplying means comprise a direct current circuitelectromagnetically engaging all of said devices at the same time.

9. The shift register circuit in accordance with claim 7 wherein aplurality of said sections comprise a stage of said shift registercircuit, and

